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cy22801 universal programmable clock generator (upcg) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-15571 rev. *e revised march 28, 2011 features integrated phase-locked loop (pll) field-programmable input frequency range: ? crystal: 8 mhz to 30 mhz ? clkin: 1 mhz to 133 mhz low-voltage complementary metal oxide semiconductor (lvcmos) output frequency: ? 1mhz to 200 mhz (commercial grade) ? 1mhz to 166.6 mhz (industrial grade) special features: ? spread spectrum ? vcxo ? inputs: pd or oe, fs low-jitter, high-accuracy outputs 3.3 v operation commercial and industrial temperature ranges 8-pin small-outline integrat ed circuit (soic) package serial interface for device configuration general description the cy22801 is a flash-programmable clock generator that supports various applications in consumer and communications markets. the device uses the cypress-proprietary pll along with spread spectrum and vcxo technology to make it one of the most versatile clock synthes izers in the market. the device uses a cypress-proprietary pll to drive up to three configurable outputs in an 8-pin soic. the cy22801 is programmed with an easy-to-use programmer dongle, the cy36800, in conj unction with the cyclocksrt? software. this enables fast sample generation of prototype builds for user-defined frequencies. logic block diagram vcxo with logic pll divider 1 divider 2 switch matrix serial i/f with control logic xin/clkin xout sdat/fs0/ vcxo/oe /pd# sclk /fs1 vcxo sdat /fs0 /pd# oe fs2 clka clkb/ fs1/ sclk clkc /fs2 ref [+] feedback
cy22801 document #: 001-15571 rev. *e page 2 of 23 contents pin configuration ............................................................. 3 external reference cr ystal/clock input ......................... 4 output clock frequencies............................................... 4 vcxo ................................................................................. 4 vcxo profile ............................................................... 4 spread spectrum clock generation (sscg) ................. 4 spread percentage ..................................................... 5 modulation frequency............. .............. .............. ........ 5 sson pin .................................................................... 5 multifunction pins ............................................................ 5 frequency calculation and register definitions ......................................................................... 5 default startup condition for the cy22801.................... 6 frequency calculations and register definitions using the serial (i2c) interface......................................................... 6 pll frequency, q counter [42h(6..0)] ....................... 8 pll frequency, p co unter [40h(1..0)], [41h(7..0)], [42h(7)] ................ .................................... 8 pll post divider options [0ch(7..0)], [47h(7..0)]....... 8 charge pump settings [40h(2..0 )] .............................. 8 clock output settings: clksrc ? clock output crosspoint switch matrix [44h(7..0)], [45h(7..0)], [46h(7..6)] ....... 9 test, reserved, and blank regi sters.......................... 9 application guideline..................................................... 11 best practices for best jitte r performance................ 11 field programming the cy22801 .................................. 11 cyclocksrt software .................................................... 11 cy36800 instaclock? kit ......... .............. .............. ......... 11 possible configuration examples ................................ 11 informational graphs ..................................................... 12 absolute maximum conditions..................................... 13 recommended operating conditions .......................... 13 recommended crystal specifications ......................... 13 pullable crystal specifications for vcxo application only.................................................. 13 dc electrical specifications ..................................................... 14 ac electrical characteristics ........................................ 14 test circuit...................................................................... 15 timing definitions .......................................................... 16 80% .................................................................................. 16 20% .................................................................................. 16 2-wire serial (i2c) interface timing............................... 17 data valid.................................................................. 17 data frame ............................................................... 17 acknowledge pulse ................................................... 17 ordering information...................................................... 19 possible configurations............................................. 19 ordering code definitions ...... ................................... 19 package diagram............................................................ 20 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design supp ort............. .......... 23 products .................................................................... 23 psoc solutions ......................................................... 23 [+] feedback
cy22801 document #: 001-15571 rev. *e page 3 of 23 pin configuration figure 1. cy22801 8-pin soic v dd cy22801 1 2 3 4 8 7 6 5 xout clkc/fs2 clka clkb/fs1/sclk xin/clkin sdat/fs0/ vcxo/oe/pd# v ss table 1. pin definition name pin number description clkin/xin 1 external reference crystal input/external reference clock input v dd 2 3.3 v voltage supply sdat/fs0/vcxo /oe/pd# 3 serial interface data line/frequency select 0 / vc xo analog control voltage / output enable / power-down v ss 4 ground clkb/fs1/sclk 5 clock output b/frequency select 1/serial interface clock line clka 6 clock output a clkc/fs2 7 clock output c / frequency select 3 / v ss xout 8 external reference crystal output: connect to ex ternal crystal. when the reference is an external clock signal (applied to pin 1), this pin is not used and must be left floating. [+] feedback
cy22801 document #: 001-15571 rev. *e page 4 of 23 external reference crystal/clock input cy22801 can accept external reference clock input as well as crystal input. external reference clock input frequency range is from 1mhz to 133 mhz. the input crystal oscillator of the cy22801 is an important feature because of the flexibility it provides in selecting a crystal as a reference clock source. the oscillator inverter has programmable gain, enabling maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. input load capacitors are placed on the cy22801 die to reduce external component cost. these capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. the value of the input load capacitors is determined by eight bits in a programmable register. total load capacitance is determined by the formula: capload = (c l ? c brd ? c chip )/0.09375 pf in cyclocksrt, enter the crystal capacitance (c l ). the value of capload is determined automatically and programmed into the cy22801. output clock frequencies the cy22801 is a very flexible clock generator with up to three individual outputs, generated from an integrated pll. see figure 2 for details. the output of the pll runs at high frequency and is divided down to generate the output clocks. two programmable dividers are available for this purpose. ther efore, although the output clocks may have different frequencies, they must be related, based on the pll frequency. it is also possible to direct the reference clock input to any of the outputs, thereby bypassing the pll. lastly, the reference clock may be passed through either divider. figure 2. basic pll block diagram vcxo one of the key components of t he cy22801 device is the vcxo. the vcxo is used to ?pull? the reference crystal higher or lower to lock the system frequency to an external source. this is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. a special pullable crystal must be used to have adequate vcxo pull range. pullable crystal spec ifications are included in this datasheet. vcxo is not compatible with spread spectrum and serial interface. vcxo profile figure 3 shows an example of a vc xo profile. the analog voltage input is on the x-axis an d the ppm range is on the y-axis. an increase in the vcxo input voltage results in a corresponding increase in the output frequency. this moves the ppm from a negative to positive offset. figure 3. vcxo profile spread spectrum clock generation (sscg) spread spectrum clock generation (sscg) in cy22801 helps to reduce emi found in today?s high-speed digital electronic systems. the device uses the proprietary spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the input clock. by modulating the frequency of the clock, the measured emi at the fundamental and harmonic frequencies is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with the regulatory agency electromagnetic compatibility (emc) requirements and improve time to market without degrading system performance. programmed spread spectrum modulation will appear same on all three clock outputs as they come from same pll even if operating at different frequenc ies. spread spectrum is not compatible with vcxo feature. clkc crosspoint switch matrix ref (xin/clkin) /p pfd vco /q clkb clka post divider 1n post divider 2n -200 -150 -100 -50 0 50 100 150 200 00.511.522.533.5 vcxo input [v] tuning [ppm] [+] feedback
cy22801 document #: 001-15571 rev. *e page 5 of 23 spread percentage the percentage of spread can be programmed from 0.25% to 2.5% for center spread and from ?0.5% to ?5.0% for down spread. the granularity is 0.25%. modulation frequency the default modulation frequency is 31.5 khz. other modulation frequencies available through configuration software are 30.1 khz and 32.9 khz. sson pin sson pin functionality can be used to turn spread on and off in clock output. any one of th e multifunction pins can be configured as sson pin. multifunction pins there are three pins with multiple functions either as control pins or as output pins. the followin g are the acronyms used for the different control function pins: output enable (oe): if oe = 1, all outputs are enabled frequency select (fs0,1,2): these pins can be used to select one of the programmed clock frequencies for clock output. all of three multifunction pins su pport this functionality. any of these pins can also be configured as spread spectrum on (sson) pin. if sson = 1, clock output has programmed spread; if sson = 0, clock output does not have spread. power-down: active low (pd#): if pd# = 0, all outputs are tristated and the device enters in the low-power state voltage controlled crystal oscillator (vcxo): analog voltage on this pin controls the outpu t frequency of oscillator serial interface clock line (sclk) and serial interface data line (sdat): these pins are for serial interface and are compatible with i 2 c. each of these three multi-f unction pins supports selected functions mentioned in ta b l e 2 . one of the supported functions can be programmed on the pin at a time. frequency calculation and register definitions the cy22801 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. they are the input reference frequency (ref), the internally calculated p and q dividers, and the post divider, which can be a fixed or calculated value. there are three formulas to determine the final output frequency of a cy22801 based design: clk = ((ref x p)/q) / post divider clk = ref / post divider clk = ref. the basic pll block diagram is shown in figure 4 . each of the three clock outputs on the cy22801 has a total of seven output options available to it. there are six post divider options available: /2 (two of these), /3, /4, /div1n and /div2n. div1n and div2n are independently calculated and are applied to individual output groups. the post divider options can be applied to the calculated vco frequency ((ref*p)/q) or to the ref directly. in addition to the six post divider output options, the seventh option bypasses the pll and pa sses the ref directly to the crosspoint switch matrix. table 2. multi function pin options pin# pin name oe pd# vcxo fs clk output i 2 c 3sdat/fs0 /vcxo/oe /pd# yyy [1] y [2] n [3] sdat [1] 5 clkb/fs1/ sclk nn ny ysclk notes 1. vcxo and sson functions as well as vcxo and serial interface functions are not compatible. 2. ?y? means pin supports this function. 3. ?n? means pin does not support this function. 4. do not use this pin as reference clock output. 7clkc/fs2n n ny y [4] n table 3. possible combinations for multifunction pins possible combinations pin#3 pin#5 pin#7 a fs0 clkb clkc b fs0 clkb fs2 c fs0 fs1 fs2 d oe/pd# clkb clkc e oe/pd# fs1 clkc f oe/pd# fs1 fs2 g sdat sclk clkc hvcxoclkbclkc table 2. multi function pin options pin# pin name oe pd# vcxo fs clk output i 2 c [+] feedback
cy22801 document #: 001-15571 rev. *e page 6 of 23 figure 4. basic block diagram of cy22801 pll default startup condi tion for the cy22801 the default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific jedec file produced by cyclocksrt ? . parts shipped from the factory are blank and unprogrammed. in this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. while you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use cyclocksrt to produce the required register setting file. the serial interface address of t he cy22801 is 69h. if there is a conflict with any other devices in your system, then this can also be changed using cyclocksrt. frequency calculations and register definitions using the serial (i 2 c) interface the cy22801 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. the i 2 c interface provides volatile programming. this means when the target system is powered down, the cy22801 reverts to its pre-i 2 c state, as defined above (programmed or unprogrammed). when the system is powered back up again, the i 2 c registers must be reconfigured again. all programmable registers in the cy22801 are addressed with eight bits and contain eight bits of data. the cy22801 is a slave device with an address of 1101001 (69h). ta b l e 4 lists the i 2 c registers and their definitions. specific register definitions and their allowable values are listed as follows. reference frequency the ref can be a crystal or a driven frequency (clkin). for crystals, the frequency range must be between 8 mhz and 30 mhz. for a driven frequency, the frequency range must be between 1 mhz and 133 mhz. programmable crystal input oscillator gain settings the input crystal oscillator gain (xdrv) is controlled by two bits in register 12h and are set according to ta b l e 5 on page 7. the parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (esr, available from the manufacturer), and the capload setting during crystal startup. bits 3 and 4 of register 12h control the input crystal oscillator gain setting. bit 4 is the msb of the se tting, and bit 3 is the lsb. the setting is programmed according to table 5 on page 7. all other bits in the register are reserved and should be programmed as shown in ta b l e 6 on page 7. ftaaddrsrc[1:0] bits set frequency tuning array address source. this will be set by cyclockrt software based on selected configuration. using an external clock as the reference input the cy22801 also accepts an external clock as reference, with speeds up to 133 mhz. with an external clock, the xdrv (register 12h) bits must be set according to table 7 on page 7. (q+2) pfd vco (2(pb+4)+po) /div1n /2 /3 /div2n /4 /2 div1n[0ch] div1src[0ch] div2src[47h] div1n[47h] clkoe[09h] ref clksrc crosspoint switch matrix divider bank 1 divider bank 2 clka clkb clkc qtotal ptotal [42h] [40h, 41h, 42h] div1clk div2clk [45h] [45h, 46h] [44h, 45h] [+] feedback
cy22801 document #: 001-15571 rev. *e page 7 of 23 table 4. summary table ? cy22801 programmable registers register description d7 d6 d5 d4 d3 d2 d1 d0 09h clkoe control 0 0 clkc clka 0 clkb 0 0 och div1src mux and div1n divider div1src div1n(6) div1n(5) div1n(4) d iv1n(3) div1n(2) div1n(1) div1n(0) 12h input crystal oscillator drive control ftaad- drsrc[1] ftaad- drsrc[0] xcapsrc xdrv(1) xdrv(0) 0 0 0 13h input load capacitor control capload (7) capload (6) capload (5) capload (4) capload (3) capload (2) capload (1) capload (0) 40h charge pump and pb counter 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) 41h pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 42h po counter, q counter po q(6) q(5) q(4) q(3) q(2) q(1) q(0) 44h crosspoint switch matrix control 111111clksrc2 for clkb clksrc1 for clkb 45h clksrc0 for clkb 1 1 1 clksrc2 for clka clksrc1 for clka clksrc0 for clka clksrc2 for clkc 46h clksrc1 for clkc clksrc0 for clkc 111111 47h div2src mux and div2n divider div2src div2n(6) div2n(5) div2n(4) d iv2n(3) div2n(2) div2n(1) div2n(0) table 5. programmable crystal input oscillator gain settings cap register settings 00h ? 80h 80h ? c0h c0h ? ffh effective load capacitance (capload) 6 pf to 12 pf 12 pf to 18 pf 18 pf to 30 pf crystal esr 30 60 30 60 30 60 crystal input frequency 8 to 15 mhz 000101100110 15 to 20 mhz 011001101010 20 to 25 mhz 011010101011 25 to 30 mhz 10 10 10 11 11 n/a table 6. crystal oscillator gain bit locations and values address d7 d6 d5 d4 d3 d2 d1 d0 12h001xdrv(1)xdrv(0)000 table 7. programmable external reference input oscillator drive settings reference frequency 1 to 25 mhz 25 to 50 mhz 50 to 90 mhz 90 to 133 mhz drive setting 00 01 10 11 [+] feedback
cy22801 document #: 001-15571 rev. *e page 8 of 23 input load capacitors xcapsrc bit in 12h register selects the source of input load capacitance. this will be set by cyclockrt software based on selected configuration. input load capacitors allow you to set the load capacitance of the cy22801 to match the input load capacitance from a crystal. the value of the input load capacitors is determined by 8 bits in a programmable register [13h]. total load capacitance is determined by the formula: capload = (c l ? c brd ? c chip )/0.09375 pf where: c l = specified load capaci tance of your crystal. c brd = the total board capacitance, due to external capacitors and board trace capacitance. in cyclocksrt, this value defaults to 2 pf. c chip = 6 pf. 0.09375 pf = the step resolution available due to the 8-bit register. in cyclocksrt, only the crystal capacitance (c l ) is specified. c chip is set to 6 pf and c brd defaults to 2 pf. if your board capacitance is higher or lower than 2 pf, the formula given earlier is used to calculate a new capload value and programmed into register 13h. in cyclocksrt, enter the crystal capacitance (c l ). the value of capload is determined automatically and programmed into the cy22801. through the sdat and sclk pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pf. for an external clock source, capload defaults to 0. see table 8 on page 9 for capload bit locations and values. the input load capacitors are placed on the cy22801 die to reduce external component cost. these capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. pll frequency, q counter [42h(6..0)] the first counter is known as the q counter. the q counter divides ref by its calculated value. q is a 7 bit divider with a maximum value of 127 and minimum value of 0. the primary value of q is determined by 7 bits in register 42h (6..0), but 2 is added to this register value to achieve the total q, or q total . q total is defined by the formula: q total = q + 2 the minimum value of q total is 2. the maximum value of q total is 129. register 42h is defined in the table. stable operation of the cy22801 cannot be guaranteed if ref/q total falls below 250 khz. q total bit locations and values are defined in table 9 on page 9. pll frequency, p counter [4 0h(1..0)], [41h(7..0)], [42h(7)] the next counter definition is the p (product) counter. the p counter is multiplied with the (ref/q total ) value to achieve the vco frequency. the product counter, defined as p total , is made up of two internal variables, pb and po. the formula for calculating p total is: p total = (2(pb + 4) + po) pb is a 10-bit variable, defined by registers 40h(1:0) and 41h(7:0). the 2 lsbs of regi ster 40h are the two msbs of variable pb. bits 4..2 of register 40h are used to determine the charge pump settings. the three msbs of register 40h are preset and reserved and cannot be changed. po is a single bit variable, defined in register 42h(7). this allows for odd numbers in p total . the remaining seven bits of 42h are used to define the q counter, as shown in table 9 . the minimum value of p total is 8. the maximum value of p total is 2055. to achieve the minimum value of p total , pb and po should both be programmed to 0. to achieve the maximum value of p total , pb should be programmed to 1023, and po should be programmed to 1. stable operation of the cy22150 cannot be guaranteed if the value of (p total *(ref/q total )) is above 400 mhz or below 100 mhz. pll post divider options [0ch(7..0)], [47h(7..0)] the output of the vco is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. the mux determines if the clock signal feeding into the divider banks is the calculated vco frequency or ref. there are two select muxes (div1src and div2src) and two divider banks (divider bank 1 and divider bank 2) used to determine this clock signal. the clock signal passing through div1src and div2src is referred to as div1clk and div2clk, respectively. the divider banks have four unique divider options available: /2, /3, /4, and /divxn. divxn is a variable that can be independently programmed (div1n and div2n) for each of the two divider banks. the minimum value of divxn is 4. the maximum value of divxn is 127. a value of di vxn below 4 is not guaranteed to work properly. div1src is a single bit variable, controlled by register 0ch. the remaining seven bits of register 0ch determine the value of post divider div1n. div2src is a single bit variable, controlled by register 47h. the remaining seven bits of register 47h determine the value of post divider div2n. register 0ch and 47h are defined in ta b l e 1 0 . charge pump settings [40h(2..0)] the correct pump setting is important for pll stability. charge pump settings are controlled by bi ts (4..2) of register 40h, and are dependent on internal variable pb (see ? pll frequency, p counter[40h(1..0)], [41h(7..0)], [42h(7)] ?). ta b l e 11 on page 9 summarizes the proper charge pump settings, based on ptotal. see table 12 on page 9 for register 40h bit locations and values. [+] feedback
cy22801 document #: 001-15571 rev. *e page 9 of 23 although using the above table guarantees stability, it is recom- mended to use the print preview function in cyclocksrt to determine the correct charge pump settings for optimal jitter performance. pll stability cannot be guaranteed for values below 16 and above 1023. if values above 1023 are needed, use cyclocksrt to determine the best charge pump setting. to configure device using serial interface, please refer cyclocksrt. clock output settings: clksrc ? clock output crosspoint switch matrix [44h(7..0)], [45h(7..0)], [46h(7..6)] every clock output can be defined to come from one of seven unique frequency sources. the clksrc(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. clksrc(2..0) is set in registers 44h, 45h, and 46h. the remainder of register 46h(5:0) must be written with the values stated in the register t able when writing register values 46h(7:6). when div1n is divisible by four, then clksrc(0,1,0) is guaranteed to be rising edge phase-aligned with clksrc(0,0,1). when div1n is six, then clksrc(0,1,1) is guaranteed to be rising edge phase-aligned with clksrc(0,0,1). when div2n is divisible by four, then clksrc(1,0,1) is guaranteed to be rising edge phase-aligned with clksrc(1,0,0). when div2n is divisible by eight, then clksrc(1,1,0) is guaranteed to be rising edge phase-aligned with clksrc(1,0,0). clkoe ? clock output enab le control [09h(5..0)] each clock output has its ow n output enable, controlled by register 09h(5..0). to enable an output, set the corresponding clkoe bit to 1. clko e settings are in table 15 on page 10. test, reserved, and blank registers writing to any of the following regi sters causes the part to exhibit abnormal behavior, as follows. [00h to 08h] ? reserved [0ah to 0bh] ? reserved [0dh to 11h] ? reserved [14h to 3fh] ? reserved [43h] ? reserved [48h to ffh] ? reserved. table 8. input load capacitor register bit settings address d7 d6 d5 d4 d3 d2 d1 d0 13h capload(7) capload(6) capload(5) capload(4) capload(3) capload(2) capload(1) capload(0) table 9. p counter and q counter register definition address d7 d6 d5 d4 d3 d2 d1 d0 40h 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) 41h pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 42h po q(6) q(5) q(4) q(3) q(2) q(1) q(0) table 10. pll post divider options address d7 d6 d5 d4 d3 d2 d1 d0 0ch div1src div1n(6) div1n(5) div1n(4) div1n(3) div1n(2) div1n(1) div1n(0) 47h div2src div2n(6) div2n(5) div2n(4) div2n(3) div2n(2) div2n(1) div2n(0) table 11. charge pump settings charge pump setti ng ? pump(2..0) calculated p total 000 16 ? 44 001 45 ? 479 010 480 ? 639 011 640 ? 799 100 800 ? 1023 101, 110, 111 do not use ? device will be unstable table 12. register 40h change pump bit settings address d7 d6 d5 d4 d3 d2 d1 d0 40h 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) [+] feedback
cy22801 document #: 001-15571 rev. *e page 10 of 23 table 13. clock output setting clksrc2 clksrc1 clksrc0 definition and notes 0 0 0 reference input. 0 0 1 div1clk/div1n. div1n is defined by regi ster [och]. allowable values for div1n are 4 to 127. if divider bank 1 is not being used, set div1n to 8. 0 1 0 div1clk/2. fixed /2 divider option. if this option is used, div1n must be divisible by 4. 0 1 1 div1clk/3. fixed /3 divider option. if this option is used, set div1n to 6. 1 0 0 div2clk/div2n. div2n is defined by regist er [47h]. allowable values for div2n are 4 to 127. if divider bank 2 is not being used, set div2n to 8. 1 0 1 div2clk/2. fixed /2 divider option. if this option is used, div2n must be divisible by 4. 1 1 0 div2clk/4. fixed /4 divider option. if this option is used, div2n must be divisible by 8. 1 1 1 reserved ? do not use. table 14. clock output register setting address d7 d6 d5 d4 d3 d2 d1 d0 44h111111clksrc2 for clkb clksrc1 for clkb 45h clksrc0 for clkb 1 1 1 clksrc2 for clka clksrc1 for clka clksrc0 for clka clksrc2 for clkc 46h clksrc1 for clkc clksrc0 for clkc 111111 table 15. clkoe bit setting address d7 d6 d5 d4 d3 d2 d1 d0 09h 0 0 clkc clka 0 clkb 0 0 [+] feedback
cy22801 document #: 001-15571 rev. *e page 11 of 23 application guideline best practices for best jitter performance jitter can be specified in different terminologies: time domain: cycle-to-cycle jitter period jitter long-term jitter frequency domain: deterministic jitter random jitter phase noise these jitter terms are usually give n in terms of root mean square (rms), peak-to-peak, or in the ca se of phase noise, dbc/hz with respect to fundamental frequency. cycle-to-cycle and period jitter are generally used terminologies. jitter depends on many factors and few of the them c an be controlled in application: input reference jitter number of active clock outputs operating temperature clock output load pll frequencies termination and layout supply voltage accuracy jitter is directly proportional to the input reference jitter, number of active clock outputs, opera ting temperature and clock output load, but inversely proportional to the pll frequency. best practices for termination, layout and supply voltage filtering are discussed in application note ?layout and termination techniques for cypress clock generators-an1111?. field programming the cy22801 the cy22801 is programmed using the cy36800 usb programmer dongle. the cy22801 is flash-technology based, so the parts are reprogrammed up to 100 times. this enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. samples and small prototype qu antities are programmed using the cy36800 programmer. cypress?s value-added distribution partners and third-party programming systems from bp microsystems, hilo systems, and others, are available for large production quantities. cyclocksrt software cyclocksrt is an easy-to-use soft ware application that enables the user to custom-configure the cy22801. users can specify the xin/clkin frequency, crystal load capacitance, and output frequencies. cyclocksrt then creates an industry-standard jedec file that is us ed to program the cy22801. when needed, an advanced mode is available that enables users to override the automatically generated voltage controlled oscillator (vco) frequency and output divider values. cyclocksrt is a component of the cyberclocks? software that you can download free of charge from the cypress website at http://www.cypress.com. cy36800 instaclock? kit the cypress cy36800 instaclock kit comes with everything needed to design the cy22801 and program samples and small prototype quantities. the cyclocksrt software is used to quickly create a jedec progra mming file, which is then downloaded directly to the portable programmer that is included in the cy36800 instaclock kit. the jedec file can also be saved for use in a production programming system for larger volumes. the cy36800 also comes with five samples of the cy22801, which are programmed with preconfigured jedec files using the instaclock software. possible configuration examples contact your local cypress field application engineer for functi onal feasibility and custom config uration with these advanced f eatures. table 16. possible configuration possible configurations pin#1 pin#3 pin#5 pin#6 pin#7 pin#8 a clkin:33 mhz oe clkb: 33 mhz clka:100 mhz with +/-1% spread sson nc bxin:27 mhz crystal vcxo pd# clka: 74.25 /74.175824 mhz fs2 xout: 27 mhz crystal c clkin:10 mhz oe fs1 clka: 25/40/33.3333/50 mhz fs2 nc d clkin:10 mhz sdat sclk clka clkb nc [+] feedback
cy22801 document #: 001-15571 rev. *e page 12 of 23 informational graphs the informational graphs are meant to convey the typical perform ance levels. no performance spec ifications is implied or guaran teed. spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= -4% 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 fnominal 0 20 40 60 80 100 120 140 160 180 200 time (us) spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= -4% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 68.5 68 67.5 67 66.5 66 65.5 65 64.5 6 4 63.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 67.5 67 66.5 66 65.5 65 64.5 [+] feedback
cy22801 document #: 001-15571 rev. *e page 13 of 23 absolute maximum conditions parameter description min max unit v dd supply voltage ?0.5 4.6 v t s storage temperature ?65 150 c t j junction temperature ? 125 c v io input and output voltage v ss ? 0.5 v dd + 0.5 v esd electrostatic discharge voltage per mil-std-833, method 3015 2000 ? v recommended oper ating conditions parameter description min typ max unit v dd operating voltage 3.14 3.3 3.47 v t a ambient temperature, commercial grade 0 ? 70 c ambient temperature, industrial grade ?40 -- 85 c c load maximum load capacitance on the clk output ? ? 15 pf t pu power-up time for v dd to reach the minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms recommended crystal specifications for non-vcxo applications parameter name description min typ max unit f nom nominal crystal frequency parallel resonance, fundamental mode, and at cut 8?30mhz c lnom nominal load capacitance 6 ? 30 pf r 1 equivalent series resistance (esr) fundamental mode ? 35 50 dl crystal drive level no external series resistor assumed ? 0.5 2 mw note 5. crystals that meet this specificati on include ecliptek ecx-5788-13.500m, siward xtl001050a-13.5-14-400, raltron a-13.500-14-c l, and pdi ha13500xfsa14xc. pullable crystal specifications for vcxo application only [5] parameter name min typ max unit c lnom crystal load capacitance ? 14 ? pf r 1 equivalent series resistance ? ? 25 r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr. ratio is used because typical r 1 values are much less than the maximum spec. 3??? dl crystal drive level. no external series resistor assumed ? 0.5 2 mw f 3sephi third overtone separation from 3 f nom (high side) 300 ? ? ppm f 3seplo third overtone separation from 3 f nom (low side) ? ? ?150 ppm c0 crystal shunt capacitance 7pf c0/c1 ratio of shunt to motional capacitance 180 ? 250 c 1 crystal motional capacitance 14.4 18 21.6 ff [+] feedback
cy22801 document #: 001-15571 rev. *e page 14 of 23 notes 6. not 100% tested, guaranteed by design. 7. power supply current is configuration de pendent. use cyclocksrt to calculate actual i dd for specific output frequency configurations. 8. skew value guaranteed when outputs are generated from the same divider bank. 9. jitter measurement may vary. actual jitter is dependent on i nput jitter and edge rate, number of active outputs, input and ou tput frequencies, supply voltage, temperature, and output load. dc electrical specifications [6] parameter name description min typ max unit i oh output high current v oh = v dd ? 0.5, v dd = 3.3 v (source) 12 24 ? ma i ol output low current v ol = 0.5, v dd = 3.3 v (sink) 12 24 ? ma c in1 input capacitance all input pins except xin and xout ? ? 7 pf c in2 input capacitance xin and xout pins for non-vcxo applications ?24?pf i ih input high current v ih = v dd ?510 a i il input low current v il = 0 v ? ? 50 a f xo vcxo pullability range using crystal in this datasheet 150 ? ppm v vcxo vcxo input range 0 ? v dd v v ih input high voltage cmos levels, 70% of v dd 0.7 v dd ??v v il input low voltage cmos levels, 30% of v dd ? ? 0.3 v dd v i dd [7] v dd supply current all three clock outputs are at 100 mhz ? 30 ? ma ac electrical characteristics parameter [6] name description min typ max unit f refc reference frequency - crystal 8 ? 30 mhz f refd reference frequency - driven 1 ? 133 mhz f out output frequency, commercial grade 1?200mhz output frequency, industrial grade 1 ? 166.6 mhz dc output duty cycle 50% of v dd, see figure 6 45 50 55 % t 3 rising edge slew rate output clock rise time, 20% - 80% of v dd, see figure 7 0.8 1.4 ? v/ns t 4 falling edge slew rate output clock fall time, 80% - 20% of v dd, see figure 7 0.8 1.4 ? v/ns t 5 [8] skew output-output skew between related outputs, see figure 9 ??250ps t 6 [9] clock jitter peak-to-peak period jitter, see figure 8 ?250?ps t ccj [ 9 ] cycle-to-cycle jitter clka/b/c xin = clka/b/c = 166 mhz, 2% spread and no refout, v dd = 3.3 v, see figure 10 ??110ps xin = clka/b/c = 66.66 mhz, 2% spread and no refout, v dd = 3.3 v, see figure 10 ??170ps xin = clka/b/c = 33.33 mhz, 2% spread and no refout, v dd = 3.3 v, see figure 10 ??140ps xin = clka/b/c = 14.318 mhz, 2% spread and no refout, v dd = 3.3 v, see figure 10 ??290ps t pd power-down time time from falling edge on pd# pin to tristated outputs (asynchronous), see figure 11 ? 150 300 ns [+] feedback
cy22801 document #: 001-15571 rev. *e page 15 of 23 test circuit figure 5. test circuit diagram t oe1 output disable time time from falling edge on oe pin to tristated outputs (asynchronous), see figure 12 ? 150 300 ns t oe2 output enable time time from rising edge on oe pin to valid clock outputs (asynchronous), see figure 12 ? 150 300 ns f mod spread spectrum modulation frequency 30.1 31.5 32.9 khz t 10 pll lock time ? ? 3 ms ac electrical characteristics (continued) parameter [6] name description min typ max unit 0.1 f v dd clk out c load gnd output [+] feedback
cy22801 document #: 001-15571 rev. *e page 16 of 23 timing definitions figure 6. duty cycle definition; dc = t2/t1 f igure 7. rise and fall time definitions figure 8. period jitter definition figure 9. skew definition figure 10. cycle to cycle jitte r definition (ccj) figure 11. power-down and power-up timing figure 12. output enable and disable timing t1 t2 clk 50% 50% t3 clk 80% 20% t4 clk 50% t6 clkx clky 50% 50% t5 t cycle_i t cycle_i+1 50% clk t ccj = t cycle_i - t cycle_i+1 (over 1000 cycles) v ih v il t pd t pu power clk down high impedance v ih v il t oe2 clk enable high impedance output t oe1 [+] feedback
cy22801 document #: 001-15571 rev. *e page 17 of 23 2-wire serial (i 2 c) interface timing when using i 2 c interface, the cy22801 should be programmed as i 2 c-capable prior to using this interface. the cy22801 uses a 2-wire serial-interface sdat and sclk that operates up to 400 kbits/seco nd in read or write mode. the basic write serial format is as follows. start bit; seven-bit device address (da); r/w bit; slave clock acknowledge (ack); eight-bit memory address (ma); ack; eight-bit data; ack; eight-bit data in ma + 1 if desired; ack; eight-bit data in ma+2; ack; and so on, until stop bit. the basic serial format is illustrated in figure 14 . data valid data is valid when the clock is high, and may only be transitional when the clock is low, as illustrated in figure 13 . data frame every new data frame is indicated by a start and stop sequence, as illustrated in figure 15 . start sequence ? start frame is indicated by sdat going low when sclk is high. every time a start signal is given, the next eight-bit data must be the device address (seven bits) and a r/w bit, followed by the register address (eight bits) and register data (eight bits). stop sequence ? stop frame is indicated by sdat going high when sclk is high. a stop frame frees the bus for writing to another part on the same bus or writing to another random register address. acknowledge pulse during write mode, the cy22801 responds with an ack pulse after every eight bits. this is accomplished by pulling the sdat line low during the n*9 th clock cycle, as illustrated in figure 16 . (n = the number of eight-bit segments transmitted.) during read mode, the ack pulse, after the data packet is sent, is generated by the master. figure 13. data valid and data transition periods figure 14. data frame architecture sdat sclk data valid transition to next bit clk low clk high v ih v il t su t dh sdat write start signal device address 7-bit r/w = 0 1-bit 8-bit register address slave 1-bit ack slave 1-bit ack 8-bit register data stop signal multiple contiguous registers slave 1-bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1-bit ack 8-bit register data (xxh+2) slave 1-bit ack 8-bit register data (ffh) slave 1-bit ack 8-bit register data (00h) slave 1-bit ack slave 1-bit ack sdat read start signal device address 7-bit r/w = 0 1-bit 8-bit register address slave 1-bit ack slave 1-bit ack 7-bit device stop signal multiple contiguous registers 1-bit r/w = 1 8-bit register data (xxh) address (xxh) master 1-bit ack 8-bit register data (xxh+1) master 1-bit ack 8-bit register data (ffh) master 1-bit ack 8-bit register data (00h) master 1-bit ack master 1-bit ack [+] feedback
cy22801 document #: 001-15571 rev. *e page 18 of 23 figure 15. start and stop frame figure 16. frame format (device address, r/w , register address, register data sdat sclk start transition to next bit stop sdat sclk da6 da5da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + table 17. two-wire serial interface parameters parameter description min max unit f sclk frequency of sclk ? 400 khz start mode time from sda low to scl low 0.6 ? s clk low sclk low period 1.3 ? s clk high sclk high period 0.6 ? s t su data transition to sclk high 100 ? ns t dh data hold (sclk low to data transition) 100 ? ns rise time of sclk and sdat ? 300 ns fall time of sclk and sdat ? 300 ns stop mode time from sclk high to sdat high 0.6 ? s stop mode to start mode 1.3 ? s [+] feedback
cy22801 document #: 001-15571 rev. *e page 19 of 23 some product offerings are factory-programmed customer -specific devices with cust omized part numbers. the possible configurations table shows the available device types, but not complete part numbers. contact your local cypress fae or sales representative for more information. ordering code definitions ordering information ordering code package type operating range operating voltage cy22801kfxc 8-pin soic commercial, 0 c to 70 c 3.3 v cy22801kfxct 8-pin soic - tape and reel commercial, 0 c to 70 c 3.3 v cy22801kfxi 8-pin soic industrial, ? 40 c to 85 c 3.3 v cy22801kfxit 8-pin soic - tape and reel industrial, ? 40 c to 85 c 3.3 v possible configurations ordering code package type operating range operating voltage cy22801ksxc-xxx [9] 8-pin soic commercial, 0 c to 70 c 3.3 v cy22801ksxc-xxxt [9] 8-pin soic - tape and reel commercial, 0 c to 70 c 3.3 v CY22801KSXI-XXX [9] 8-pin soic industrial, ? 40 c to 85 c 3.3 v CY22801KSXI-XXXt [9] 8-pin soic - tape and reel industrial, ? 40 c to 85 c 3.3 v t = tape and reel, blank = tube dash code (only for fact ory programmable devices) temperature range: c = commercial, i = industrial pb-free, blank = leaded programming option: f = field programmable, blank = factory programmable fixed value: k part identifier company id: cy = cypress xxxxx cy k (x) (-xxx) t f x notes 10. ordering codes with ?xxx? are factory-programmed configurations . factory programming is available for high volume orders. fo r more details, contact your local cypress field application engineer or cypress sales representative. [+] feedback
cy22801 document #: 001-15571 rev. *e page 20 of 23 package diagram figure 17. 8-pin (150-mil) soic sz08 51-85066 *d [+] feedback
cy22801 document #: 001-15571 rev. *e page 21 of 23 acronyms document conventions units of measure table 18. acronyms used in this documnent acronym description acronym description ack acknowledge pd power down clkin clock input pfd phase frequency detector emi electromagnetic interference pll phase locked loop esd electrostatic discharge sson spread spectrum on emc electromagnetic compatibility sclk serial interface clock fs frequency select sdat serial interface data i 2 c inter integrated circuit ssc spread spectrum clock jedec eia joint electron device engineering council electronic industries alliance vco voltage controlled oscillator lvcmos low-voltage complementary metal oxide semiconductor vcxo voltage controlled crystal oscillator oe output enable , table 19. units of measure symbol unit of measure symbol unit of measure c degrees celsius vrms microvolts root-mean-square db decibels w microwatts dbc/hz decibels relative to the carrier per hertz ma milliamperes fc femto coulomb mm millimeters ff femto farads ms milliseconds hz hertz mv millivolts kb 1024 bytes na nanoamperes kbit 1024 bits ns nanoseconds khz kilohertz nv nanovolts k kilohms ohms mhz megahertz pa picoamperes m megaohms pf pico farads a microamperes pp peak-to-peak f microfarads ppm parts per million h microhenrys ps picoseconds s microseconds sps samples per second v microvolts sigma: one standard deviation [+] feedback
cy22801 document #: 001-15571 rev. *e page 22 of 23 document history page document title: cy22801 universal programmable clock generator (upcg) document number: 001-15571 revision ecn orig. of change submission date description of change ** 1058080 kvm/ kkvtmp 05/10/07 new data sheet *a 2440787 aesa 05/16/08 updated template. added note 9 and 10 . added existing part numbers cy22801fxct, cy22801fxi, cy22801fxit, cy22801sxc-xxx and cy22801sxc-xxxt in ordering info rmation table. added new part numbers cy22801kfx c, cy22801kfxct, cy22801kfxi, cy22801kfxit, cy22801ksxc-xxx and cy22801ksxc-xxxt. *b 2724806 kvm/ aesa 6/26/09 add industrial grade ambient te mperature to recommended operating conditions. add separate fout max limit for industrial temp. add temperature ranges to the ordering information table. remove cy22801fxct and cy22801fxit from ordering information table. add CY22801KSXI-XXX and CY22801KSXI-XXXt to ordering information table. correct package reference from s8 to sz08. *c 2897775 kvm 03/23/10 removed inactive parts from the ordering information table. moved xxx parts to possible configurations table.updated package diagram *d 2981862 bash 07/15/2010 features : added ss, vcxo, fs, pd, oe removed benefits section from page 1. updated logic block diagram , pin configuration , and pin definition added sscg and vcxo description, frequency calculation and register definitions, multi function pin options and possible configurations sections added information graphs of spread spectrum added serial interface description added crystal specs for vcxo added vcxo specs in dc specifications table added ctcj, pd and oe timing in ac char table added and ordering code definitions . added crystal part numbers in footnote ?a? on page 13. *e 3207656 cxq 03/28/2011 changed t dh min spec from 0 ns to 100 ns. [+] feedback
document #: 001-15571 rev. *e revised march 28, 2011 page 23 of 23 cyclocksrt, cyberclocks, and instaclock are trademarks of cypress se miconductor corporation. all products and company names men tioned in this document may be the trademarks of their respective holders. cy22801 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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